VARIUS -
Process Variation Model
Parameter variation poses a major challenge to
high-performance microprocessor design, negatively
impacting a processor’s frequency and leakage power.
To study the impact of variation, as well as stimulate the
development of microarchitectural solutions to reduce its
impact, we developed a microarchitecture-level model for
process variation.
The alpha version of the model can be
downloaded here. For more details on the model
please see the following papers:
Smruti R. Sarangi, Brian Greskamp, Radu Teodorescu, Jun
Nakano, Abhishek Tiwari and Josep Torrellas, VARIUS: A
Model of Parameter Variation and Resulting Timing Errors
for Microarchitects, IEEE Transactions on Semiconductor
Manufacturing (IEEE TSM), February 2008 [pdf]
Radu Teodorescu, Brian Greskamp, Jun Nakano, Smruti R.
Sarangi, Abhishek Tiwari and Josep Torrellas, VARIUS: A
Model of Parameter Variation and Resulting Timing Errors
for Microarchitects, Workshop on Architectural Support for
Gigascale Integration (ASGI), in conjunction with ISCA,
June 2007 [pdf]
Some papers where the model is used:
Radu Teodorescu and Josep Torrellas, Variation-Aware
Application Scheduling and Power Management for Chip
Multiprocessors, 35th International Symposium on Computer
Architecture (ISCA), June 2008 [pdf]
Radu Teodorescu, Jun Nakano, Abhishek Tiwari and Josep
Torrellas, Mitigating Parameter Variation with Dynamic
Fine-Grain Body Biasing, 40th
International Symposium on Microarchitecture (MICRO),
December 2007 [pdf]
Abhishek Tiwari, Smruti Sarangi, Josep Torrellas, ReCycle:
Pipeline Adaptation to Tolerate Parameter Variation, 34th
Annual International Symposium on Computer Architecture
(ISCA), June 2007 [pdf]
