CSE675.02: Introduction
to Computer Architecture - Fall 2008
Instructor:
Radu Teodorescu
Office:
783 Dreese Labs
Office hours:
Wednesday 1-2:30pm
(tentative)
Email:
{teodores} in CSE at Ohio
State
Grader:
Jin He
Office:
274 Dreese
Labs
Office hours: 1-2:30pm
Tuesday and Thursday
Email: {he.146} at
OSU
Class days, time and location: M, Tu, W, and F, 3:30-4:18,
BO 0428
Link to course website: www.cse.ohio-state.edu/~teodores
Please use the Carmen CSE675 forum for discussions on
lectures, homework. Do not
post homework solutions -
that is considered cheating!
Description:
Computer system components,
instruction set design, performance metrics, arithmetic
algorithms/circuits, floating point operations, datapath
and control unit design, memory and an introduction to I/O
interfaces.
Objectives:
To give students an
understanding of the hardware components of a computer and
to provide students with an appreciation of trade-offs in
designing a processor and main memory.
Prerequisites:
CSE360 or ECE265, Math 366
Textbook:
“Computer Organization
& Design: The Hardware/Software Interface,
Third
Edition”, D.A.
Patterson & J.L. Hennessy, 2005 by Elsevier Inc.
Grading:
* Homework 35% (7-8 assignments)
* Midterm Exam 25% (in class)
* Final Exam 35% (comprehensive)
* Class Participation & Attendance 5%
Homework must be turned in at the beginning of class
on the date
due. Late homeworks
can be accepted only if preapproved.
Tentative Class
Schedule
| Date | Topic | Notes | Reading Assignments | Homework |
|---|---|---|---|---|
| 09/24/08 | 1. Introduction | (slides) | H&P Chapter 1 | |
| 09/26/08 | 2. MIPS Architecture and ISA | Part 1 (slides) | H&P Chapter 2.1-2.9 | |
| 09/29/08 | (cont'd) | Part 2 (slides) | MIPS ISA Handout | |
| 09/30/08 | (cont'd) | Part 3 (slides) | H&P Chapters 3.1,3.2, A.7, A.10 | |
| 10/01/08 | 3. Computer Performance Metrics | (slides) | H&P Chapter 4 | |
| 10/03/08 | (cont'd) | HW1 Out, Due 10/10, Solutions | ||
| 10/06/08 | (cont'd) | |||
| 10/07/08 | 4. Introduction to Digital Logic Design | Part 1 (slides) | H&P Chapters B.1, B.2, B.3 | |
| 10/08/08 | (cont'd) | |||
| 10/10/08 | (cont'd) | HW2 Out, due 10/17, Solutions | ||
| 10/13/08 | (cont'd) | Part 2 (slides) | H&P Chapters B.7, B.8 | |
| 10/14/08 | (cont'd) | |||
| 10/15/08 | (cont'd) | |||
| 10/17/08 | 5. Main Memory and Register File Design | Part 1 (slides) | H&P Chapter B.9 | HW3 Out, due 10/24, Solutions |
| 10/20/08 | (cont'd) | MIPS Register File | ||
| 10/21/08 | (cont'd) | |||
| 10/22/08 | (cont'd) | |||
| 10/24/08 | Midterm review | |||
| 10/27/08 | MIDTERM! | |||
| 10/28/08 | Main Memory and Register File Design (cont'd) | Part 2 (slides) | Memory design examples | |
| 10/29/08 | (cont'd) | |||
| 10/31/08 | (cont'd) | HW4 Out, due 11/07 | ||
| 11/03/08 | 6. Arithmetic Logic Unit | Part 1 (slides) | H&P Chapter B.5 | |
| 11/04/08 | (cont'd) | |||
| 11/05/08 | (cont'd) | Part 2 (slides) | H&P Chapters 3.4, 3.6 | |
| 11/07/08 | 8. Designing the MIPS Microprocessor (single cycle) | Slides | H&P Chapters 5.1-5.4 | HW5 Out, due 11/14 |
| 11/10/08 | NO CLASS (out of town) | |||
| 11/12/08 | (cont'd) | |||
| 11/14/08 | (cont'd) | HW6 Out, due 11/25, Solutions | ||
| 11/17/08 | 9. Designing the MIPS Microprocessor (multi-cycle) | Slides | H&P Chapters 5.5, 5.6 | |
| 11/18/08 | NO CLASS (giving a talk) | |||
| 11/19/08 | (cont'd) | |||
| 11/21/08 | (cont'd) | |||
| 11/24/08 | (cont'd) | |||
| 11/25/08 | 10. Advanced Memory Organizations | Slides | H&P Chapter 7 | |
| 11/26/08 | (cont'd) | |||
| 12/01/08 | (cont'd) | |||
| 12/02/08 | (cont'd) | |||
| 12/03/08 | (cont'd) | |||
| 12/05/08 | Final Exam Review | |||
| 12/11/08 | FINAL EXAM! 3:30 to 5:18 in class |