The Computer Architecture Research Lab at Ohio State University is focused on developing the next generation energy efficient multicore architectures that meet the challenges of increasingly unreliable technology. More details on our research are available here.
This year we are graduating an excellent Ph.D. student, Timothy Miller. He is looking for positions in academia or industry research. Please check out his resume and visit his website for details.
We are organizing the weekly Architecture Reading Group.
News:
04/27/2012 Congratulations to Tim for successfully defending his PhD thesis. First PhD graduate in our group. Well done Doctor!
04/15/2012 Renji will be spending the summer at Intel's Technology for Reliability and Usage group in Hudson, Massachusetts.
03/02/2012 Our paper on characterizing and eliminating voltage emergencies in many-core processors will appear in ISCA 2012.
01/12/2012 Tim won our department’s Graduate Student Research Award for 2012! The award if given to two Ph.D. students every year for exceptional research accomplishments. Congratulations!
11/09/2011 Our paper on reducing variation effects in near-threshold chip multiprocessors was accepted at HPCA 2012. Congratulations team!
08/01/2011 Our group received an NSF GOALI grant to support our research on ultra-low power architectures. The project is an academia/industry collaboration between our research group and Mentor Graphics.
07/14/2011 Congratulations to Tim to successfully defending his Candidacy proposal and to Xiang for passing his Qualifiers through the accelerated option!
06/17/2011 Congratulations to Naser for having his paper accepted at PACT!
12/07/2010 Tim delivered a great presentation at MICRO! The slides are available here.
08/17/2010 Our paper on error correction for near-threshold caches was accepted to MICRO 2010. Congratulations to all involved!
07/26/2010 We had a paper accepted to SBAC-PAD 2010. Congratulations to Tim and Naga!
Selected publications:
- *new* VRSync: Characterizing and Eliminating Synchronization-Induced Voltage Emergencies in Many-core Processors, International Symposium on Computer Architecture (ISCA), June 2012
- *new* Booster: Reactive Core Acceleration for Mitigating the Effects of Process Variation and Application Imbalance in Low-Voltage Chips, International Symposium on High-Performance Computer Architecture (HPCA), February 2012
- *new* Mitigating the Effects of Process Variation in Ultra-low Voltage Chip Multiprocessors using Dual Supply Voltages and Half-Speed Units, IEEE Computer Architecture Letters (CAL), 2012
- *new* StVEC: A Vector Instruction Extension for High Performance Stencil Computation, International Conference on Parallel Architectures and Compilation Techniques (PACT), October 2011
- Parichute: Generalized Turbocode-Based Error Correction for Near-Threshold Caches, International Symposium on Microarchitecture (MICRO), December 2010
- Flexible Error Protection for Energy Efficient Reliable Architectures, International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), Petrópolis, Brazil, October 2010
- Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors, International Symposium on Computer Architecture (ISCA), June 2008
- VARIUS: A Model of Parameter Variation and Resulting Timing Errors for Microarchitects, IEEE Transactions on Semiconductor Manufacturing (IEEE TSM), February 2008
- Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing, International Symposium on Microarchitecture (MICRO), December 2007