- Week 1 - C.1 -
Design
Issues of Parallel Architectures
(Parallel Architectures, Convergence of Parallel
Architectures, and Fundamental Design Issues.)
2 Slides/page
6 Slides/page
An Overview of the Upcoming 10PF Blue Waters Project
Overview Slides
- Week 2 - D.1 and D.2 - Interconnection Network Design Principles
(Classification of interconnection networks, basic switching techniques,
virtual channels.)
2 Slides/page (D1)
2 Slides/page (D2)
- Week 3 - D.3, D.4, and D.5 - Design Principles (Cont'd) and
Collective Communication Support
(Deadlock, Livelock, and Starvation; Routing Algorithms for direct,
indirect, and switch-based networks;
System support,
hardware implementations, and software implementations
for collective communication)
2 Slides/page (D3)
2 Slides/page (D4)
2 Slides/page (D5)
- Weeks 4, 5 and 6 - Trends in Designing Next Generation Systems
Multi-core Architecture
(Intel, AMD MagnyCours, nVIDIA GPGPU, Intel MIC, etc.)
Prof. Marc Snir's presentation at UPCRC Summer School, 2009
Inside Intel Core Microarchitecture: Setting New Standards for Energy-Efficient Performance
Dr. Bob Kuhn's presentation at UPCRC Summer School, 2009
AMD Magny-Cour Architecture
High Performance Computing with CUDA, Part of Supercomputing '09 Tutorial
Intel ManyIntegrated Core (MIC) Architecture
AMD Fusion Architecture
IBM Blue Gene Series Architectures
Overview of Blue Gene Hardware Architecture
Overview of Blue Gene Software Architecture
Cray XT5 and XE6 systems and Interconnects (Seastar and Gemini)
Overview of Cray Jaguar Architecture
Overview of Cray Seastar Interconnect
Cray XE Systems
On-Chip Interconnect
2006 Workshop on On- and Off-Chip Interconnection Networks
for Multicore Systems
Future Directions for On-Chip Interconnection Networks
- Weeks 7 and 8 - C.5 - Design of Shared-Memory Multiprocessors
(Cache Coherence, Memory Consistency, Snooping Protocols,
Protocol Design Tradeoffs, Synchronization, and Implications
on Software.)
2 Slides/page (C5)
- Week 9 - C.6 - Snoop-based Multiprocessor
(Symmetric Multiprocessor) Design
(Single-level cache with an atomic bus, multi-level cache
hierarchies and split-transaction bus.)
2 Slides/page (C6)
- Week 10 - C.8 and C.9 - Overview of Designing Scalable Systems
DSM Systems with
Directory-based Cache Coherence and Software DSM Systems
(Directory-based approach and tradeoffs, Memory-based and
Cache-based directory protocols, and synchronization.
Software DSM Systems)
Scalable Non Cache Coherent Systems Supporting PGAS Models
2 slides/page (C8)
