Syllabus for 875 (Advanced Computer Architecture) (Sp '08)

Class Syllabus for 875 (Advanced Computer Architecture, Sp '08)

We will be covering the following chapters/topics from the textbooks. The chapters of the first book are identified as C.x (C standing for Culler) and the chapters of the second book as D.x (D standing for Duato). Additional papers from the literature will also be included.

Week 1 - C.1 - Design Issues of Parallel Architectures
(Parallel Architectures, Convergence of Parallel Architectures, and Fundamental Design Issues.)
2 Slides/page
6 Slides/page
Week 2 - D.1 and D.2 - Interconnection Network Design Principles
(Classification of interconnection networks, basic switching techniques, virtual channels.)
2 Slides/page (D1)
6 Slides/page (D1)
2 Slides/page (D2)
6 Slides/page (D2)
Week 3 - D.3, D.4, and D.5 - Design Principles (Cont'd) and Collective Communication Support (Deadlock, Livelock, and Starvation; Routing Algorithms for direct, indirect, and switch-based networks; System support, hardware implementations, and software implementations for collective communication)
2 Slides/page (D3)
6 Slides/page (D3)
2 Slides/page (D4)
6 Slides/page (D4)
2 Slides/page (D5)
6 Slides/page (D5)
Weeks 4, 5 and 6 - Trends in Designing Next Generation Systems
(Multi-core Architecture (Cell, Sun Niagara, Intel TeraFlop), On-Chip Interconnect, IBM Blue Gene Architecture, Systems being developed under DARPA's HPCS Program)
Papers from the literature will be provided.
Overview of Blue Gene Hardware Architecture
Overview of Blue Gene Software Architecture
Overview of BlueGene/P Architecture

Intel Multi-Core Processors: Making the Move to Quad-Core and Beyond
Inside Intel Core Microarchitecture: Setting New Standards for Energy-Efficient Performance
Barcelona: AMD's Next Generation Quad-Core Microprocessor

Cell Multiprocessor Communication Network; Built for Speed
Summit on Software and Algorithms for the Cell Processor

Niagara-2: A Highly-Threaded Server-on-a-Chip

2006 Workshop on On- and Off-Chip Interconnection Networks for Multicore Systems
DARPA HPCS Program's Web Page
Weeks 7 and 8 - C.5 - Design of Shared-Memory Multiprocessors
(Cache Coherence, Memory Consistency, Snooping Protocols, Protocol Design Tradeoffs, Synchronization, and Implications on Software.)
2 Slides/page
6 Slides/page
Week 9 - C.6 - Snoop-based Multiprocessor (Symmetric Multiprocessor) Design
(Single-level cache with an atomic bus, multi-level cache hierarchies and split-transaction bus.)
2 Slides/page
6 Slides/page
Week 10 - C.8 and C.9 - Overview of Designing Scalable DSM Systems with Directory-based Cache Coherence and Software DSM Systems
(Directory-based approach and tradeoffs, Memory-based and Cache-based directory protocols, and synchronization. Software DSM Systems)
C8_Slides (2 slides/page)
C8_Slides (6 slides/page)

Last Updated: May 20, 2008