775: Computer Architecture
Autumn 2008
Instructor: Prof. Dhabaleswar K. Panda
Office: DL 785, Tel: 2-5199
E-mail:panda@cse.ohio-state.edu
Office Hours: MW 11:30am-12:20pm
Grader: Yuan Hong
Office: DL 786
E-mail: hongy@cse.ohio-state.edu
Office Hours: TR 4:00-5:00pm or by appointment
Class Hours:
MW 12:30-1:48pm (DL 357)
Prerequisite:
CSE 675 and CSE 660
Course Objectives:
- To understand and appreciate the principles and tradeoffs
(cost/performance, speed/flexibility) behind
the design of modern computer systems in a qualitative and
quantitative fashion.
- To understand issues in choosing and designing an instruction set.
- To learn the concepts of basic pipelining and advanced pipelining
techniques.
- To understand issues lated to multithreading and instruction-level
parallelism.
- To learn issues related to hierarchical memory system design.
- To obtain an overview of parallel computer architectures.
Textbook:
Computer Architecture: A Quantitative Approach by
John Hennessy and David Patterson, Morgan Kauffman,
2007 (Fourth edition).
Grading Plan:
There are four components:
Homeworks (4x5) (20%)
Simulation Labs (6+8+6) (20%)
Midterm exam (25%)
Final exam (35%)
Homeworks:
There will be four
problem sets. Due dates (tentatives)
are mentioned in the class schedule. Homeworks need to be
turned in at the begining of the class when they are due.
The problem sets will be distributed
before one week of the due date. Late homeworks are not encouraged.
An exception to this rule requires that you have a strong and convincing
reason. If you have such a reason, you will have to let me
know about it in advance. Homework solutions will be distributed
within one-two weeks after the due date. Absolutely, no
homeworks will be accepted after the solutions are distributed.
Labs using Simulators:
There will be three
labs involving simulation experiments.
The labs will involve using SimpleScalar simulators to evaluate
instruction statistics, pipelining techniques and branch mechanisms,
and memory behavior on contemporary benchmark suites (SPEC).
The labs will be distributed around 10 days in advance.
All simulators run on the CSE SUN Solaris systems.
The labs need to be done individually unless otherwise noted.
Each student has been assigned an account in the CSE system
to carry out these simulation.
If you do not have an account please let me know about it.
I strongly suggest getting familiarized with these simulator
environments as early as possible (hence the attached simulator description).
The simulator and benchmarks
are located at (/usr/class/cse775/newsim).
Detailed guidelines to carry out these labs
will be provided with the homeworks and lab handouts.
Examinations:
There will be two examinations.
A midterm will be held on the 12th class
and a final at the end of the quarter, as indicated below.
Examinations are closed book, closed notes, and
closed neighbors.
MIDTERM Wednesday, Oct 29th, 12:30pm - 1:45pm (in class)
FINAL Monday, Dec 8th, 11:30am - 1:30pm (in class)
Electronic Distribution of Class Materials:
During the first week of the class, I will collect e-mail
addresses of all students
to create an electronic mailing list.
Make sure that you give me your e-mail address (campus or work)
on the system
you frequently log on.
If you do not receive any e-mail from me by the second week of
the class, please check with me to ensure that your name is in the mailing
list.
I will use this mailing list throughout the quarter to make
important announcements and clarifications about homework problems,
if needed.
Class Slides
- Course Overview:
1 slide/page ,
2 slides/page ,
6 slides/page
- Chapter 1:
1 slide/page ,
2 slides/page ,
6 slides/page
- Appendix B:
1 slide/page ,
2 slides/page ,
6 slides/page
- Appendix A:
1 slide/page ,
2 slides/page ,
6 slides/page
- Chapter 2:
1 slide/page ,
2 slides/page ,
6 slides/page
- Chapter 5 and Appendix C:
1 slide/page ,
2 slides/page
6 slides/page
-
Intel Multi-Core Processors: Making the Move to Quad-Core and Beyond
-
Inside Intel Core Microarchitecture: Setting New Standards for Energy-Efficient
Performance
-
First the Tick, Now the Tock: Next Generation Intel Microarchitecture (Nehlam)
-
Barcelona: AMD's Next Generation Quad-Core Microprocessor
Homeworks and Labs:
PDF copies of homeworks and labs will be available here as the
quarter progresses.
An e-mail announcement will be made when each homework is placed
on the Web.