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Schedule

CSE775: Computer Architecture - Autumn 2011

Monday and Wednesday at 12:30-1:48PM in Dreese Labs 305

Lecture notes, homework assignments and class management will be done through Carmen.


Professor Christopher Stewart (http://www.cse.ohio-state.edu/~cstewart)
Office:
793 Dreese Labs
Office hours: Monday 2-2:30pm  (or by appointment)
Email: {cstewart} at cse dot ohio dash state dot edu

Grader: Zhezhe Chen
Office hours:
  by appointment
Email:
  chenzhe@cse.ohio-state.edu

Primary Textbook:
“Computer Architecture: A Quantitative Approach, Fourth Edition”, J.L. Hennessey and D.A. Patterson, 2007 by Elsevier Inc.


Grading:

Homework 20% There will be 4 homework asssignments.  Each will count for 5% of the final grade.
Midterm Exam 30% The midterm will be in class.
Final Exam 40% The final will be comprehensive.
Research Exposure
10% Summaries of 4 research papers on computer architcture will be worth 2.5% each.


Letter grades will be assigned as follows:
93%--A
90%--A-
87%--B+
83%--B
80%--B-
77%--C+
73%--C
70%--C-
67%--D+
63%--D
60%--D-

Grade changes:
Students seeking a grade change should submit a 1-paragraph write up explaining their dispute to the TA within 1 week of recieving the disputed grade.  Any disputes that reach the teacher without going through this process will be summarily dismissed.

Academic Misconduct:
Cheating on exams, copying homework assignments, or plagarizing in any way are a violation of the school's policy on academic misconduct.  Violators will be reported to the Dean of Academic Affairs and risk expulsion.

Topics covered

* To understand and appreciate the principles and tradeoffs (cost/performance, speed/flexibility) behind the design of modern computer systems in a qualitative and quantitative fashion.
* To understand issues in choosing and designing an instruction set.
* To learn the concepts of basic pipelining and advanced pipelining techniques.
* To understand issues lated to multithreading and instruction-level parallelism.
* To learn issues related to hierarchical memory system design.
* To obtain an overview of parallel computer architectures.