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Research


I graduated with a Ph.D. on Aug 24, 2008. This website will however prevail for one more year. I now work at the IBM Watson Research Labs, Yorktown Heights, New York.

I work on parallelizing compilers for multi-core processors (and sometimes for accelerators like GPGPUs and FPGAs). In general, my research interests are in compiler optimizations and their interactions with advances in computer architecture and programming model design. I am advised by Prof. P. Sadayappan.

Research software/tools

PLUTO

Ph.D. thesis

Effective Automatic Parallelization and Locality Optimization using the Polyhedral Model [PDF | PS] (pre-print)
Defended Aug 4th, 2008.

Conference Publications

BibTeX

  1. A Practical Automatic Polyhedral Parallelizer and Locality Optimizer [PS | PDF | Slides]
    Uday Bondhugula, A. Hartono, J. Ramanujan, P. Sadayappan.
    ACM SIGPLAN Programming Languages Design and Implementation (PLDI), Jun 2008, Tucson, Arizona.

  2. Automatic Transformations for Communication-Minimized Parallelization and Locality Optimization in the Polyhedral Model [PS | PDF | Slides]
    Uday Bondhugula, M. Baskaran, S. Krishnamoorthy, J. Ramanujam, A. Rountev, and P. Sadayappan.
    International Conference on Compiler Construction (ETAPS CC), Apr 2008, Budapest, Hungary.

  3. A Compiler Framework for Optimization of Affine Loop Nests for GPGPUs [PDF]
    Muthu Baskaran, Uday Bondhugula, J. Ramanujam, A. Rountev, and P. Sadayappan.
    ACM International Conference on Supercomputing (ICS), Jun 2008, Island of Kos, Greece.

  4. Automatic Data Movement and Computation Mapping for Multi-level Parallel Architectures with Explicitly Managed Memories.
    Muthu Baskaran, Uday Bondhugula, S. Krishnamoorthy, J. Ramanujam, A. Rountev, and P. Sadayappan.
    ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP), Feb 2008, Salt Lake City, Utah.

  5. Effective Automatic Parallelization of Stencil Computations [PS | PDF]
    S. Krishnamoorthy, M. Baskaran, Uday Bondhugula, J. Ramanujam, A. Rountev, and P. Sadayappan.
    ACM SIGPLAN Programming Language Design and Implementation (PLDI), Jun 2007, San Diego, California.

  6. Automatic Mapping of Nested Loops to FPGAs [PS | PDF | Talk]
    Uday Bondhugula, J. Ramanujam, and P. Sadayappan.
    ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP), Mar 2007, San Jose, California.

  7. Hardware/Software Integration for FPGA-based All-Pairs Shortest-Paths [PS | PDF | Talk]
    Uday Bondhugula, A. Devulapalli, James Dinan, J. Fernando, Pete Wyckoff, E. Stahlberg, and P. Sadayappan.
    IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '06), Apr 2006, Napa Valley, California.

  8. Parallel FPGA-based All-Pairs Shortest-Paths in a Directed Graph [PS | PDF | Talk]
    Uday Bondhugula, Ananth Devulapalli, Joseph Fernando, Pete Wyckoff, and P. Sadayappan.
    20th IEEE International Parallel & Distributed Processing Symposium (IPDPS '06), Apr 2006, Rodos, Greece.

  9. High Performance RDMA-based All-to-all Broadcast for InfiniBand Clusters [PS | PDF]
    S. Sur, Uday Bondhugula, A. Mamidala, H.-W. Jin, and D. K. Panda.
    12th IEEE International Conference on High Performance Computing (HiPC '05), Dec 2005.

Research Reports

  1. PLUTO: A Practical Automatic Polyhedral Parallelizer and Locality Optimizer [PS | PDF]
    Uday Bondhugula, J. Ramanujam, and P. Sadayappan.
    OSU Research Report OSU-CISRC-10/07-TR70.

  2. Affine transformations for communication minimal parallelization and locality optimization of arbitrarily nested loop sequences [PS | PDF]
    Uday Bondhugula, M. Baskaran, S. Krishnamoorthy, J. Ramanujam, A. Rountev, and P. Sadayappan.
    OSU Research Report OSU-CISRC-5/07-TR43.

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